circuit MyRoutingArbiter :
  module MyRoutingArbiter :
    input clock : Clock
    input reset : UInt<1>
    output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<8>}[4], out : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<8>}}

    node _io_out_valid_T = or(io.in[0].valid, io.in[1].valid) @[MyRoutingArbiter.scala 13:47]
    node _io_out_valid_T_1 = or(_io_out_valid_T, io.in[2].valid) @[MyRoutingArbiter.scala 13:47]
    node _io_out_valid_T_2 = or(_io_out_valid_T_1, io.in[3].valid) @[MyRoutingArbiter.scala 13:47]
    io.out.valid <= _io_out_valid_T_2 @[MyRoutingArbiter.scala 13:16]
    node _channel_T = mux(io.in[2].valid, UInt<2>("h2"), UInt<2>("h3")) @[Mux.scala 47:70]
    node _channel_T_1 = mux(io.in[1].valid, UInt<1>("h1"), _channel_T) @[Mux.scala 47:70]
    node channel = mux(io.in[0].valid, UInt<1>("h0"), _channel_T_1) @[Mux.scala 47:70]
    io.out.bits <= io.in[channel].bits @[MyRoutingArbiter.scala 17:15]
    node _io_in_0_ready_T = eq(channel, UInt<1>("h0")) @[MyRoutingArbiter.scala 19:38]
    node _io_in_0_ready_T_1 = and(io.out.ready, _io_in_0_ready_T) @[MyRoutingArbiter.scala 19:27]
    io.in[0].ready <= _io_in_0_ready_T_1 @[MyRoutingArbiter.scala 19:11]
    node _io_in_1_ready_T = eq(channel, UInt<1>("h1")) @[MyRoutingArbiter.scala 19:38]
    node _io_in_1_ready_T_1 = and(io.out.ready, _io_in_1_ready_T) @[MyRoutingArbiter.scala 19:27]
    io.in[1].ready <= _io_in_1_ready_T_1 @[MyRoutingArbiter.scala 19:11]
    node _io_in_2_ready_T = eq(channel, UInt<2>("h2")) @[MyRoutingArbiter.scala 19:38]
    node _io_in_2_ready_T_1 = and(io.out.ready, _io_in_2_ready_T) @[MyRoutingArbiter.scala 19:27]
    io.in[2].ready <= _io_in_2_ready_T_1 @[MyRoutingArbiter.scala 19:11]
    node _io_in_3_ready_T = eq(channel, UInt<2>("h3")) @[MyRoutingArbiter.scala 19:38]
    node _io_in_3_ready_T_1 = and(io.out.ready, _io_in_3_ready_T) @[MyRoutingArbiter.scala 19:27]
    io.in[3].ready <= _io_in_3_ready_T_1 @[MyRoutingArbiter.scala 19:11]

